1. Field of the Invention
The present invention relates to a decoder circuit and, more particularly, to a decoder circuit adopting the concept of a neural network.
2. Description of the Prior Art
In digital systems, information including data and instructions, is transmitted as binary levels or pulse trains. If, for example, four bits are assigned to determine an instruction, it is possible to have 16 different instructions. The instructions are coded in the two digit binary system.
Further, digital systems can be thought to operate similarly to a plurality of two position switches. For example the positioning of the switches would be set according to the binary coded data. In other words, each unique setting of the switches would constitute a unique instruction and it is necessary that only a single specific setting of the switches correspond to a specific single one of the 16 instruction codes.
The process which identifies a specific instruction code is called decoding. In conventional decoder circuits a great number of components (gates) are required to handle an input of four bits and decode therefrom any one of 16 different instructions. Moreover, with conventionally designed decoder circuits, as the number of input bits increases (for a greater number of instructions), the number of gates needed during the decoding process also greatly increases.
Thus, conventional decoder circuits have several associated problems, such as increased power consumption and decreased access time. These problems are caused by enlargement of the chip area, which results from the increased number of bits and gates needed to code and decode the instructions.